TMSC 54 Digital MSPx1xx Family User Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. ES1 or ES2 is marked on the package as part of the device number. See the example below.
|Published (Last):||22 November 2010|
|PDF File Size:||14.91 Mb|
|ePub File Size:||17.69 Mb|
|Price:||Free* [*Free Regsitration Required]|
TMSC 54 Digital MSPx1xx Family User Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. ES1 or ES2 is marked on the package as part of the device number. See the example below. Contact your local Cypress Sales Representative if you have questions. Room Temperature Functionality. Note Errata items in the table below are hyperlinked.
Click on any item entry to jump to its description. Items 1. Device Features 2. Power System Initialization 8. Power System Requirements 9. Device Function Boost Converter Operation at Low Voltage Vdda Monotonicity I2C Clocking CAN Conformance SWD Clock I2C Hardware Address Match VDAC0 Operation Analog Connectivity USB Suspend Interrupts Oscillator Fail-Detect VDAC Output DMA Termination Analog Routing Electrical Specifications Segment LCD Drive Device Latch Up Vddio0, Vddio1 Voltage Range Boost Converter in Low Power Mode They are disabled by default.
Keep in their disabled state. The device will stay in the low power mode and stop responding to all other stimulus if a WDT reset occurs in the low power mode. Do not use the WDT and low power modes in the same application.
If low power modes and the WDT must be used in the same application, ensure that the device wakes from the low power mode and the WDT is serviced before a WDT reset can occur. Setting the LVD and comparator interrupt modes to edge mode has no effect.
If sleep or idle low power modes are entered and if the central timewheel is not already enabled, increased wake times or low voltage reset may occur.
Central timewheel time settings are not critical. The power consumption of sleep and hibernate modes is higher than specified in ES1 silicon. A ES1 Silicon 1? A ES2 Silicon nA ? Silicon revision fix available in ES3 for active mode. September 7, Document Number: Rev. APIs are provided that implement the specific code sequences required for this version of the silicon. A non monotonic region of decreasing voltage during this period causes the device to delay startup.
Startup may be delayed for several minutes. No device damage occurs due to this issue. If the result is truncated to n bits, the maximum count is the same as the minimum count.
It is interpreted as the minimum count creating a discontinuity. Instead the range is 0x80 to 0x80 to The recommended workaround is to read and use at least one more bit of resolution from ADC than the configured conversion requires. The extra bit ensures that the sign is properly accounted for. For 6 and 7 bit conversions read an int8 value, for 8 to 15 bit conversions read an int16 value, for greater than 15 bit conversions read an int The second workaround is to ensure that the maximum count value is never reached by the ADC in the end application.
Glitch filtering does not meet certification requirements. Electrically noisy environment. Affects testing and certification for production. If the component with this instance name does not experience an output voltage greater than 2.
If the component with this instance name does require an output greater than 2. Click the add directive icon. No additional Vddio current will occur when not in the high current region even if the trigger condition is met. No other features of the SIO pin are impacted. Higher current is seen during the brief transition period through the high current region from high to low logic levels if the trigger condition is met. This will minimize the duration of the extra Vddio current.
If MHz crystal accuracy is required with Vdda below 2. If the application requires digital pins to be driven to a voltage less than Vbias, the SIO pins can be used in regulated output mode and GPIO pins can be configured for open drain, drives low mode, and driven high with a pull up to the required voltage.
This errata exists in both ES1 and ES2 silicon. This issue affects ES1 and ES2 silicon. If USB is disabled on the device no errata exists. The use of Alternate Active mode verse Sleep or Hibernate for the workaround results in increased current of ? For hardware updates, the hardware strobe always outputs the previously strobed data.
If an error occurs the XERR bit will not reflect the error condition. The glitch is noticed more prominently when it is buffered due to the low output impedance of the buffer. Glitches can be reduced by not buffering the VDAC output or by adding capacitance to the output to filter the glitches. This issue only applies when performing manual analog routing with direct register writes.
PSoC Creator currently implements the required workaround. No user intervention is required. Calling the Start API sets the bit. Calling the Stop API does not clear the bit. This may result in an ISR becoming executed multiple times for a single interrupt condition.
This issue does not apply when using an external clock. Instead, it stays in weak drive mode. If large enough, the DC offset may create contrast fluctuations and over time, damage to the LCD glass.
The effect of the DC offset is directly impacted by the size and electrical properties of the glass panel being driven. This can occur at any value of Vdd voltage.
Under certain conditions, simply touching the pin with a long wire is sufficient to cause device latch up. In one application, it is possible to use an opamp as a comparator; the opamp's output can be routed through the pin and back into the DSI for further processing.
The pin must be configured as an input with CMOS logic levels. This feature still works, as long as nothing is connected to the pin. If restrictions are not met, the device does not operate.
Vddio0 must be greater than or equal to Vddio1, which must be greater than or equal to Vddd. No device damage will occur. This issue impacts ES1 silicon. The dedicated low side CapSense switch signal and switch are not used. If the VIDACs are not enabled, current will flow through the analog routing, causing offsets and measurement errors. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
Configurable Blocks, PSoC® 3
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement.
Datasheet ID: CY8CKIT-003A 508172
CY8C3866AXI-040 Original Stock & Competitive Price